Frequency detectors are used in a wide variety of circuits, such as, for example, phase locked loop (PLL) circuits in which the frequency range of the oscillator exceeds the pull-in range of the phase detector. The frequency detector must be able to 1) detect both the magnitude and polarity of the frequency difference, and 2) yield to the phase detector once the frequency error is determined to be within a small range (also referred to as the dead-band region). When the circuit is operating in or near phase lock, any glitch or false indication from the frequency detector dead-band indicator could cause the PLL to lose lock. Current dead-band detectors produce glitches due to metastability, which then causes the PLL to temporarily lose lock.
A typical clock and data recovery circuit (CDR) contains both a frequency and phase detector circuit. The circuit is composed of two loops, with either a phase locked loop or a frequency acquisition loop active at one time. A multiplexor, controlled by the frequency detector, selects either the frequency acquisition loop or the phase locked loop. The dead-band detection circuit typically resides in the frequency detection circuit and is key to determining which loop is active (in control) at a particular time. If the dead-band circuit gives a false indication or produces a glitch, the PLL is broken and the circuit could drift out of phase lock. This type of circuit is described in A. Pottbacker, et al., “A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gb/s”, IEEE Journal of Solid-State Circuits, Vol. SC-27, pp. 1747-1751, 1992.
Frequency detectors typically operate by comparing an unknown frequency to a known or reference frequency. In the case of the prior art circuit in FIG. 1, the frequency detector compares the VCO frequency to the reference frequency Fref. It is typical for the reference frequency to be close, but not equal to, the desired operating frequency. Since the desired frequency can be different from the reference frequency, the frequency detector must be able to compare two signals that are asynchronous. In order for a digital frequency detector to compare two asynchronous signals, one must sample the other. This circuit is sometimes referred to as a synchronizer.
There have been many papers written having as their premise that a perfect synchronizer is impossible to build due to the metastability of the latching circuit, J. M. Rabaey, Digital Integrated Circuits, Prentice Hall, 1996, pp. 533-538; B. Wu, et al., “Oversampling Rotational Frequency Detector”, U.S. Pat. No. 6,055,286. With one asynchronous signal sampling another (assuming both have finite rise times), the sampling signal will at some times sample the transition of another. This means that the sampled signal is neither a logic 1 nor a logic zero, but somewhere between. Any latching circuit will have a balance point where for any input signal above this point, a logic 1 is latched and below this point, a logic 0 is latched. This point is called the metastable point. The regenerative nature of latching circuits causes any sampled signal to diverge from the metastable point exponentially with time. The output voltage after the sampling instant can be described as v(t)=VMS+(v(0)−VMS)et/τ where VMS is the metastable voltage, v(0) is the initial voltage, and τ is the regenerative time constant of the latch. From this equation, the time it takes to reach a voltage VFS the full-scale voltage, is given by   t  =            τln      ⁡              (                                            V              FS                        -                          V              MS                                                          ν              ⁡                              (                0                )                                      -                          V              MS                                      )              .  
From this equation, it can be seen that the time it takes to resolve an input signal goes to infinity as v(0) approaches VMS. The time it takes is also proportional to the time constant of the latch. This means the probability of a sampled signal not resolving to a known logic level is decreased the longer the latch regenerates and the lower the time constant of the latch. The problem with metastability is that a signal that has not resolved to a known state can branch to multiple paths. Each path could interpret the signal in a different way, causing an erroneous output.
Common methods for synchronization involve adding delay (usually through a cascade of latches) and using latches with small time constants to reduce the probability that a signal has not regenerated to a known level. Both methods have drawbacks. The more latches that are added, the larger the power and area consumed. For most common circuit technologies, more power is needed to reduce the time constant of a given latch topology.
One solution to the frequency acquisition problem in clock and data recovery circuits, and particularly for phase-locked loop control, is shown in Wu, et al., U.S. Pat. No. 6,055,286, issued Apr. 25, 2000, which patent is hereby incorporated by reference herein.